DDR4/DDR5 Routing Calculator
DDR4 | DDR5 | LPDDR4/5
Review routing guidance for DDR memory interfaces. Differential calculation is temporarily unavailable; use a validated coupled-line solver for clock and strobe pairs.
DDR Data Rates and Impedance Targets
| Standard | Data Rate |
|---|---|
| DDR4-2400 | 2400 MT/s |
| DDR4-3200 | 3200 MT/s |
| DDR5-4800 | 4800 MT/s |
| DDR5-6400 | 6400 MT/s |
Impedance targets for DDR depend on the memory controller or SoC platform, the topology and the DRAM generation. There is no single value for all DDR4/DDR5 designs, so none is stated here; take the single-ended and differential targets from your SoC/PHY vendor's PCB design guideline and the memory vendor's datasheet.
DDR Signal Groups & Requirements
Data Signals (DQ/DQS)
- • DQ: single-ended; impedance target from your SoC/PHY guideline
- • DQS/DQS#: differential pair; target from your SoC/PHY guideline
- • Length match DQ to DQS within byte lane
- • Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
- • Route as tight groups by byte lane
Address/Command (ADDR/CMD)
- • Address: single-ended; target from your SoC/PHY guideline
- • Command: single-ended; target from your SoC/PHY guideline
- • Length match to clock
- • Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
- • T-topology or fly-by routing
Clock (CK/CK#)
- • CK/CK#: differential pair; target from your SoC/PHY guideline
- • Reference signal for ADDR/CMD
- • Route with matched lengths
- • Keep away from noisy signals
- • Consider termination strategy
Control Signals
- • CS#, CKE, ODT: single-ended; target from your SoC/PHY guideline
- • Reset#: Standard GPIO
- • Check timing requirements in your SoC/PHY datasheet
- • Match to clock group
- • Standard routing rules apply
DDR PCB Design Guidelines
Length Matching
Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
Fly-By Topology
DDR4/5 uses fly-by topology for ADDR/CMD/CLK. Signals visit each DIMM/chip in sequence. Write leveling compensates for timing skew.
Termination
Check your SoC/PHY and memory datasheets for on-die termination (ODT) and external termination requirements for your configuration.
Review Your DDR Stackup
Enter your own stackup (dielectric height, Er, and copper thickness) in the impedance calculator for isolated-line single-ended estimates, because trace width depends on stackup. Differential calculation is temporarily unavailable.
DDR Design FAQ
What impedance for DDR4?
There is no single impedance for all DDR4 designs: the single-ended and differential targets depend on the memory controller or SoC platform and the topology. Take them from your SoC/PHY vendor PCB guideline and the memory datasheet. This page does not state them, nor tolerance and skew budgets.
How tight should length matching be?
Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
What's fly-by topology?
DDR4/5 routes clock and address signals to each memory chip in sequence (not parallel). Write leveling compensates for the resulting timing skew.
Do I need special PCB materials for DDR?
Check the current interface specification and your SoC/PHY datasheet for PCB material requirements for your channel.
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