PCIe Impedance Calculator
PCIe 3.0 | PCIe 4.0 | PCIe 5.0 | PCIe 6.0
Review routing guidance for PCI Express. Numeric differential calculation is temporarily unavailable; confirm pair geometry with a validated field solver and your fabricator.
PCIe Data Rates and Nominal Impedance
| PCIe Version | Transfer Rate | Bandwidth/Lane | Nominal Differential Z |
|---|---|---|---|
| PCIe 3.0 | 8 GT/s | ~1 GB/s/lane | 85Ω |
| PCIe 4.0 | 16 GT/s | ~2 GB/s/lane | 85Ω |
| PCIe 5.0 | 32 GT/s | ~4 GB/s/lane | 85Ω |
| PCIe 6.0 | 64 GT/s | ~8 GB/s/lane | 85Ω |
PCIe PCB Design Guidelines
85Ω Differential
The nominal differential impedance target for PCIe is 85Ω; confirm coupled-pair geometry independently.
AC Coupling
Check the current PCIe specification and your SoC/PHY datasheet for AC coupling requirements and capacitor placement.
Length Matching
Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
Version-Specific Considerations
PCIe 3.0
- • 85Ω nominal differential target
- • Check PCB material requirements in your SoC/PHY datasheet
- • 8 GT/s, NRZ encoding
- • Check channel length constraints in your SoC/PHY datasheet
- • Check the current PCIe specification for your design
PCIe 4.0/5.0/6.0
- • Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
- • Check PCB material requirements in your SoC/PHY datasheet
- • Check via design constraints for your channel
- • Check channel length constraints in your SoC/PHY datasheet
- • PCIe 6.0 uses PAM4 encoding
Definitions and References
PCI Express is a point-to-point interconnect standard used to move high-speed digital traffic between a host and peripheral devices. A wire harness is an organized bundle of wires, terminals, and protective coverings used to route power or signals between assemblies, while cable assembly refers to a prepared cable or grouped cables that are terminated for a defined interconnect job.
Review Your PCIe Stackup
Use the impedance calculator for isolated-line single-ended estimates. Differential width and spacing calculations are temporarily unavailable; use a validated coupled-line solver.
Source note: the impedance values on this page are the nominal targets commonly cited for this interface. This site does not reproduce the standard's text and has not verified them against it. Confirm them, with tolerances and skew budgets, in the PCI Express base and CEM specifications for your generation (PCI-SIG) and your SoC/PHY datasheet.
PCIe Design FAQ
What is the nominal impedance target for PCIe?
The nominal differential impedance target is 85Ω. Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
Do I need low-loss materials?
Check the current interface specification and your SoC/PHY datasheet for PCB material requirements for your channel.
How important are AC coupling capacitors?
Check the current PCIe specification and your SoC/PHY datasheet for AC coupling requirements and capacitor placement.
What about via design for PCIe?
Check the current PCIe specification and your SoC/PHY datasheet for via design constraints for your channel.
Should I calculate both width and spacing?
Yes. PCIe differential impedance depends on the full geometry, including width, spacing, dielectric height, copper thickness, and reference planes.
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