USB Trace Width Calculator
USB 2.0 | USB 3.0/3.1/3.2 | USB 4.0
Review routing guidance for USB. Numeric differential calculation is temporarily unavailable; confirm pair geometry with a validated field solver and your fabricator.
What this page can and cannot tell you
USB high-speed pairs are routed as controlled differential pairs with a 90 Ω nominal target; trace width and spacing depend on your stackup. This page does not compute a numeric result for this topic. Take the pair geometry from your fabricator's impedance stackup or a validated field solver.
Assumptions
- The 90 Ω figure is the commonly cited nominal differential target for USB; this site has not verified it against the specification text.
Limits
- Numeric differential calculation is switched off until it is validated against a field solver or published source.
USB Nominal Impedance Targets
| USB Version | Max Speed | Nominal Differential Impedance | Signaling |
|---|---|---|---|
| USB 2.0 | 480 Mbps | 90Ω | Differential |
| USB 3.0/3.1 | 5/10 Gbps | 90Ω | Differential |
| USB 3.2 | 20 Gbps | 90Ω | Differential |
| USB 4.0 | 40/80 Gbps | See current USB4 specification | Differential |
USB PCB Design Guidelines
90Ω Differential
Use the USB interface specification to set the differential target and a validated coupled-line solver to determine width and spacing. The available single-ended result is for an isolated line.
Length Matching
Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
Reference Planes
Route USB signals over continuous ground planes. Avoid splits or gaps that could cause impedance discontinuities and signal reflections.
USB Version Design Considerations
USB 2.0 High-Speed
- • 90Ω differential impedance
- • Single differential pair (D+/D-)
- • Check routing constraints in your SoC/PHY datasheet
- • Check channel length constraints in your SoC/PHY datasheet
- • Check PCB material requirements in your SoC/PHY datasheet
USB 3.0+ SuperSpeed
- • 90Ω differential for each pair
- • Multiple differential pairs (TX/RX)
- • Check skew budgets in the current interface specification
- • Loss budget considerations
- • Check PCB material requirements for your channel
Review Your USB Stackup
Use the impedance calculator for isolated-line single-ended estimates. Differential width and spacing calculations are temporarily unavailable; use a validated coupled-line solver.
Source note: the impedance values on this page are the nominal targets commonly cited for this interface. This site does not reproduce the standard's text and has not verified them against it. Confirm them, with tolerances and skew budgets, in the current USB specification for your speed class (USB-IF) and your SoC/PHY datasheet.
USB Design FAQ
What impedance do I need for USB?
The nominal differential impedance target is 90Ω. Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them. Isolated-line Z0 is not an odd-mode or differential result; validate the coupled pair separately.
What's the max USB trace length?
Check the current interface specification and your SoC/PHY datasheet for channel length constraints; this page does not state a trace-length limit.
Do I need controlled impedance for USB 2.0?
Check the current USB specification and your SoC/PHY datasheet for controlled-impedance requirements. Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
How tight should length matching be?
Tolerance and intra-pair / inter-pair skew budgets are defined in the current interface specification and your SoC/PHY datasheet; check them there. This page does not state them.
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